The continuous increase of the IC integration level requires the device size to be constantly reduced in proportion. But sometimes the working voltage of the electric apparatus remains unchanged, and the actual electric field strength inside the MOS device continuously increases. The high electric field causes a series of reliability problems and degrades the device performance. For example, the parasitic series resistance between the source and drain regions of the MOSFET decreases the equivalent working voltage.
FIG. 1 illustrates an MOSFET in the prior art where the heavily doped source/drain has metal silicide. In which, a gate stacked structure 20 is formed on a substrate 10, the gate stacked structure 20 is composed of a gate dielectric layer 21 and a gate electrode 22. The gate stacked structure 20 is taken as a mask to perform a first source/drain ion implantation to form a lightly doped source/drain (LDD) region or a source/drain extension region 31. Next, isolation sidewall spacers 40 are formed on both sides of the gate stacked structure 20. The isolation sidewall spacer 40 is taken as a mask to perform a second source/drain ion implantation to form a heavily doped source/drain region 32. Next, through the self-aligned silicide procedure, a source/drain contact 50 of the metal silicide is formed on the heavily doped source/drain region 32 on each side of the isolation sidewall spacer 40. To be noted, In FIG. 1 and subsequent drawings, sometimes for the convenience of illustration, only the structures on the bulk silicon substrate are shown, but the present invention is still adaptive to the Silicon-on-Insulator (SOT) substrate. For example in FIGS. 4 to 8, the bulk silicon substrate is shown on the left side of the Shallow Trench Isolation (STI), and the SOI substrate is shown in the right side. The above two substrates are not directly connected to each other, and only shown for the convenience of illustration.
In order to be brief, only the left half structure of the MOSFET device is shown. In which, as illustrated in the drawing, the source/drain parasitic series resistance Rsd is composed of four resistances connected in series, i.e., a resistance Rov of the overlapped part of the source/drain extension region 31 and the gate stacked structure 20, a resistance Rext of the source/drain extension region 31, a resistance Rdp of the heavily doped source/drain region 32 below the source/drain contact 50, and a contact resistance Rcsd between the source/drain contact 50 and the heavily doped source/drain region 32, namely Rsd=Rcsd+Rdp+Rext+Rov. With the continuous development of the technology node, the device size continuously decreases, while those resistances will increase with the reduction of the device size. In which the contact resistance Rcsd is especially important and plays an increasingly significant role. For example, in the device with a physical grid length less than 53 nm, the contact resistance Rcsd occupies more than 60% of the whole source/drain parasitic series resistance Rsd.
As shown in Table 1, according to the technology road map of 2010, the allowed maximum contact resistance of the Totally Depleted SOI (FDSOI) device will reach an order of 10−9 Ω-cm2, which brings a great challenge to the device design and manufacturing.
TABLE 1Year2015201620172018201920202021Technology node (nm)222017.715.714.012.511.1physical grid length (nm)17151412.811.710.79.7maximum contact resistance of4.0 × 10−82.0 × 10−81.0 × 10−88.0 × 10−97.0 × 10−96.0 × 10−95.0 × 10−9FDSOI (Ω*cm2)
As can be seen from the conductive mechanism between the metal and the semiconductor (e.g., n-type semiconductor), the contact resistance is a function between the height and width of the barrier. In case the semiconductor has a low doping concentration and a high Schottky Barrier Height (SBH), the conductive mechanism is the thermionic emission, and a Schottky contact occurs between the metal and the semiconductor. In case the semiconductor has an intermediate doping concentration and an intermediate SBH, the conductive mechanism is a combination of the thermionic and field emissions, and the contact between the metal and the semiconductor falls in between the Schottky contact and the ohmic contact. In case the semiconductor has a high doping concentration and a low SBH, the conductive mechanism is the field emission, and an ohmic contact occurs between the metal and the semiconductor; in that case, the electrons can easily go beyond the barrier, i.e., the contact resistance is low. It is clear that in order to reduce the contact resistance Rcsd, an ohmic contact must be produced between the metal and the semiconductor.
The magnitude of the contact resistance Rcsd depends on its resistivity ρc. Regarding the ohmic contact, ρc is proportional to the functions related to the SBH, the doping concentration and the effective carrier mass, as shown in the following mathematical expression (1):
                              ρ          c                ∝                  ⅇ                      (                                                            2                  ⁢                                                                          ⁢                                      ϕ                    B                                                  ℏ                            ⁢                                                                                          ɛ                      s                                        ⁢                                          m                      *                                                        N                                                      )                                              (        1        )            
In which, ρc is the resistivity of the contact resistance Rcsd, ΦB is the SBH, N is the source/drain doping concentration, and m* is the effective carrier mass.
As can be seen from mathematical expression (1), there are mainly three methods for decreasing the contact resistance Rcsd by reducing ρc:
1. Increasing the source/drain region doping concentration N, e.g., increasing the implantation dose, expanding interface impurity distribution by laser annealing, improving the source/drain to increase the source/drain junction depth, etc.
2. Reducing the SBH ΦB, e.g., using different metal silicide materials depending on different types (NMOS and PMOS) to reduce electron ΦB in the NMOS and cavity ΦB in the PMOS, respectively (i.e., the double-silicide process).
3. Reducing the effective carrier mass m* by a band gap engineering (or design), e.g., using narrow band gap materials such as Si1-xGex in the source/drain region.
However, the above three methods are very limited.
Regarding Method 1, due to the limited solid solubility of dopant or impurities in the silicon, the doping concentration N of the source/drain region cannot be continuously increased, i.e., N has a maximum value.
Regarding Method 2, due to different silicide materials, different layouts shall be made and different metal materials shall be deposited based on different types (NMOS and PMOS) when the MOS is manufactured. Thus the process complexity is greatly increased and the method cannot be applied in the actual production.
Regarding Method 3, it seems a simple process to just change the source/drain region material, but the doping concentration of impurities in Si1-xGex is lower than that in Si, i.e., although m* is reduced, N is also deceased, and there is no obvious reduction of ρc of the whole device.
Based on the prior art and by means of strict theoretical derivations and experimental verifications, the applicant employs a silicide as the doping source to reduce the SBH, so as to reduce the source/drain contact resistance using the above Method 2. Specifically, referring to FIGS. 1 to 3, the method may comprise: as illustrated in FIG. 1, a metal silicide 50 (usually Nickel-based metal silicide) is formed on the heavily doped source/drain region 32 having an LDD structure 31. As illustrated in FIG. 2, an ion implantation is performed for the metal silicide 50; for NMOS, the doping ions comprise N, P, As, O, S, Se, Te, F, Cl and combinations thereof, and for PMOS, the doping ions comprise B, Al, Ga, In and combinations thereof. As illustrated in FIG. 3, a driving annealing is performed so that the doping ions are segregated at the interface between the metal silicide and the source/drain region to form a segregation region 60 of the doping ions, which can effectively reduce the SBH, thereby decreasing resistivity of the contact resistance, and hence the device performance is improved.
However, the above method that reduces the SBH using the SADS still has the following deficiency: impurity ions implanted into the source/drain of the Nickel-based metal silicide have a poor solubility, and the implanted large quantity of ions cannot be solid-soluble in the Nickel-based metal silicide, thus the number of the doping ions available for reducing the SBH is not enough. By means of grain boundary diffusion, the implanted ions are segregate at the interface between the Nickel-based metal silicide and the silicon of the source/drain region to form a condensation region. But the temperature of the driving annealing is low and is not sufficient to completely activate the segregated impurities, thus the SBH is not obviously reduced. Therefore, the above conventional method is not enough to reduce the SBH to a level below 0.1 eV.
In summary, the existing MOSFET cannot effectively reduce the SBH, and then cannot effectively decrease the source/drain resistance RCSD while effectively improving the driving capability of the device. Thus the electric properties of the semiconductor device are seriously influenced, and it emergently requires a semiconductor device capable of effectively reducing the SBH and a method for manufacturing the same.